Low power optimization in the area of integrated circuits ("ICs") is a known goal. Numerous tools exist for IC designers, including designers of microprocessors, to optimize their designs for low power. In addition, tools have been described to assist programmers of software to be executed on microprocessors to optimize instruction selection for low power.
For example, in an article entitled, "Power Analysis of Embedded Software: A First Step Towards Software Power Minimization," by Vivek Tiwari, et al., IEEE Trans. on VLSI Systs., Vol. 2, No. 4, December, 1994, a methodology is proposed for instruction level power modeling in which the current drawn by a microprocessor is measured. The authors suggest that simulation based power analysis tools might be used in generating CPU models, without indicating how that might be done in any practical scale. In fact, for embedded system design the authors pointed out problems they believed would exist in attempting such an approach. Instead, the authors recommended a methodology based on laboratory measurements of CPU power consumption during execution of selected instructions. Based on such measurements, the authors propose a model in which the total IC power consumption is broken down into components such as "base energy cost," "inter-instruction effects," "effects of resource constraints," etc. These components are provided for each instruction in a program, and summed, to yield an estimated power consumption for the program.
In a subsequent article entitled, "Power Analysis of a Programmable DSP for Architecture/Program Optimization," by Hirotsugu Kojima, et al., ICSPAT Conf., 1995, the authors propose a power modeling methodology based on power analysis of a digital signal processor ("DSP") using switch level and cell based simulation. The authors draw certain conclusions in their paper about relative contributions to overall power consumption of the DSP under analysis of, e.g., clock and bus circuits vs. data path. No proposals are made as to practical application of any results to software optimization, however.
In U.S. Pat. No. 5,557,557, entitled "Processor Power Profiler," which issued on Sep. 17, 1996, to Gene A. Frantz, et al., and which is commonly assigned, a method is presented for determining the energy consumption of a processor when executing a program. The method is embodied in a power profiler program, and initially selects the processor which will execute the program. It then creates a model of energy used by the processor as a function of a plurality of instructions operable by the processor. The model is constructed based on measurements of the processor current taken under various controlled conditions. The program whose energy consumption is to be determined is then executed using the energy model to determine the energy consumption of the program on the processor. The energy model relates information regarding instruction opcodes, data values, processor environment, etc., to power data provided by a processor simulator or evaluator program, and adds the power data. The method groups certain instructions by common power considerations, and so partitioning of instructions is done in an early phase of the method, to take advantage of this grouping.
The patent to Frantz, et al. provides an excellent method for power analysis of a microprocessor at the instruction level. However, there is a desire for a method for power analysis of a microprocessor with expanded capabilities, for even greater accuracy.